Comparator:

Vclk mclk 0 PULSE(0 5 0 100u 100u 5000u 10000u)
VVA VA 0 DC=1.5
VVE VE 0 DC=2.5
VRESET RESET 0 DC=5

* Transiant Response *
.PROBE
.TRAN 100u 2000




TestCir:

Vclk mclkPIN 0 PULSE(0 5 0 1n 1n 500u 1000u)
Vscan scanPIN 0 DC=0
Vtest testPIN 0 DC=0
Vreset resetPIN 0 PWL(0 0 0 5 20ms 0)
Vstart floorplan_0/sar_0/start 0 PWL(0 0 0 0 25ms 5 35ms 0)
Vhi vupPIN 0 DC=15
Vlo vdownPIN 0 DC=0
Vin viPIN 0 DC=8

* Transiant Response *
.PROBE
.TRAN 1u 20000u

sar:

Vclk clk 0 PULSE(0 5 0 1n 1n 500u 1000u)

Vscan SCAN_IN 0 DC=0
Vtest TEST 0 DC=0
VRESET reset 0 PWL(0 0 0 5 5000u 5 5010u 0)
Vstart start 0 DC=5
* PWL(0 0 0 0 25000u 0 25100u 5 35000u 5 35100 0)
Vgt gt 0 DC=5


* Transient Response *
.PROBE
.TRAN 1u 20000u